Google Reportedly Brings AMD Into Next-Generation TPU Design

Google is reportedly working with AMD on a 10th-generation Tensor Processing Unit project, potentially bringing CPU technology and advanced chip packaging into a future version of its in-house AI accelerator.

The claim emerged in a SemiAnalysis note for clients and was reported by Tom’s Hardware on Sunday 16 August. Neither Google nor AMD has publicly confirmed the reported arrangement, and there is no confirmed product, launch date, production schedule or commercial agreement.

According to Tom’s Hardware’s account of the SemiAnalysis note, the proposed work concerns a TPU project in the v10 generation. The report suggests AMD could contribute CPU intellectual property, advanced packaging and potentially other integration technology to a design that puts CPU cores on the same package as Google’s AI accelerator.

“Market chatter suggests [Google] is working with AMD on a TPU project in the v10 generation.”

That wording matters. It is market chatter reported through a client note, not a formal announcement from either company. Details that would normally establish how significant such a partnership is — including the processor architecture, number of CPU cores, chip manufacturing process, memory, performance and power figures — have not been confirmed.

A possible change in TPU design

The reported focus is on reinforcement learning, reasoning and agentic AI workloads. These differ from conventional large-model training or straightforward inference because they can require frequent switching between accelerator-heavy calculations and more general-purpose control tasks.

In broad terms, placing CPU capability closer to the TPU could reduce the amount of data that has to move between separate processor and accelerator components. That may reduce communication overhead in workloads where the two must interact regularly. However, no performance benefit for a potential AMD-assisted TPU has been confirmed.

SemiAnalysis reportedly argued that AMD’s CPU technology and packaging experience could be useful here. Tom’s Hardware quoted the note as saying: “AMD has strong IP, especially in advanced packaging and SoIC. Additionally, CPU IP could also be a draw given Google and its customers are pushing for TPUs with on-package CPU cores for RL workloads.”

SoIC was mentioned in the report as part of AMD’s advanced-packaging expertise, but it is not confirmed that this technology would be used in a Google TPU. Nor is it known whether AMD would provide a complete CPU design, packaging support, interconnect technology, or a combination of these elements.

Where Google’s TPUs stand today

Google’s latest publicly announced TPU family is its eighth generation, unveiled on 22 April 2026. The company introduced TPU 8i for inference, post-training, reasoning and reinforcement learning, while TPU 8t is aimed at large-scale training. Google described the pair as hardware built for the “agentic era”.

Google says TPU 8i offers an 80% performance-per-dollar improvement over previous generations for low-latency inference on large mixture-of-experts models. It says TPU 8t supports superpods of up to 9,600 chips and delivers nearly three times the compute performance per pod of the preceding generation. Both products were listed as “Coming soon” on Google Cloud’s TPU page when reviewed.

Those eighth-generation systems already show Google’s interest in treating the host processor and accelerator as part of a wider platform. Google says TPU 8i and TPU 8t run with its Axion ARM-based CPU host, allowing it to optimise the system beyond the accelerator alone.

Tom’s Hardware reported that TPU 8i systems use roughly one Axion CPU for every two TPUs, compared with a reported one Intel Xeon processor for every four TPUs in seventh-generation systems. The publication also said some workloads may favour a one-to-one CPU-to-accelerator ratio, though that is industry reporting rather than a Google specification.

A TPU with CPU cores integrated into the same package would be a further step beyond that system-level pairing. It could make sense for AI systems designed to plan, reason, use tools and repeatedly respond to changing information rather than simply process a prompt and return an answer.

What AMD’s role could mean

Google has historically designed TPU architecture while working with external implementation partners. Tom’s Hardware described Broadcom as Google’s silicon-design partner for earlier TPU generations. The reported AMD role, if it materialises, could therefore give AMD a more direct place in custom AI accelerator development rather than simply supplying off-the-shelf CPUs or GPUs.

SemiAnalysis reportedly described this as potentially AMD’s first major involvement in a custom AI ASIC project, despite the company having a custom silicon team. The note said: “AMD's involvement would be the first real involvement in a custom AI ASIC project, despite having a custom silicon team.”

That does not establish who would do what on a final product. The division of work between Google, AMD, Broadcom, a manufacturing partner and any packaging supplier has not been disclosed. It is also unclear whether the project will result in a commercial TPU generation at all.

What happens next

For now, Google’s publicly announced roadmap remains focused on TPU 8i and TPU 8t, while its seventh-generation Ironwood TPU is listed as generally available. There is no public TPU v10 announcement, and no indication of when such a chip could be made, deployed in Google Cloud or offered to customers.

The next meaningful development would be confirmation from Google or AMD. Until then, the report is best viewed as an indication of where hyperscale AI hardware may be heading: tighter combinations of general-purpose compute, specialised accelerators and advanced packaging for increasingly demanding AI workloads.